Senior RTL Design Engineer

About the team About the role

The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with

About the role

SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture

Required Qualifications

B.S. in Electrical Engineering, Computer Engineering, or Computer Science

5+ years of experience in ASIC RTL design

Solid foundation in computer architecture and digital logic design

Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs

Experience making design decisions that trade off power, performance, and area

Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR

Experience with digital logic synthesis tools and static timing analysis

Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking

Experience implementing SystemVerilog Assertions to check design intent

Familiarity with tools and simulators for hardware performance analysis and tuning

Familiarity with Git for managing release cycles

Scripting skills in Python and Linux shell

Preferred Qualifications

M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science

Exposure to a full ASIC development cycle through tape-out and production silicon

Interest in or knowledge of AI workload acceleration techniques

Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes

Exposure to emulation or FPGA prototyping platforms for pre-silicon validation

Base Salary Range:

Base Pay Range

$120,000—$200,000 USD