Director of ASIC Design Verification

About the team

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The DV team verifies SambaNova's RDU chips before they tape out. That covers block, full-chip, and gate-level benches, performance verification, coverage closure, and emulation and FPGA prototyping. When first silicon comes back, the same engineers debug bring-up in the lab.

About the role

SambaNova Systems is looking for a Director of ASIC Design Verification to own end to end verification for the next generation of our RDU chips. This role asks for genuine depth in verification, not just management of it. You'll be the technical authority on methodology as well as the leader of the team.

You'll set verification architecture and strategy across the full chip and be accountable for pre-silicon quality through tape-out. The work spans block through full-chip and gate-level benches, performance verification, coverage closure, and emulation and FPGA prototyping. You'll be the DV voice in roadmap and tape-out readiness decisions, and your ownership carries into first silicon, supporting functional validation and bring-up debug in the lab.

You'll lead an experienced team of 8-10 engineers, including principal-level engineers who have built and evolved our verification environment across several generations of silicon. That depth is the most valuable thing you inherit. You'll own where the environment goes next, including the decision to change it, and we expect you to arrive with a point of view. You'll also own the team's growth, leveling, and technical bar as our silicon roadmap scales.

Responsibilities

Some of your responsibilities will include:

Own verification through tape-out

Own pre-silicon functional and performance verification for SambaNova ASICs — quality, coverage closure, and on-time delivery to tape-out

Define verification architecture, strategy, schedules, and DV environments for complex, high-performance machine learning ASICs

Serve as the technical authority on verification: arbitrate testbench architecture, set coverage and sign-off criteria, and lead debug on the hardest failures

Set and defend the DV schedule and own tape-out readiness sign-off, including the trade-off between coverage depth and time to silicon; report risk and readiness to executive staff with a clear point of view, not just a dashboard

Carry ownership into first silicon — support lab functional validation and bring-up debug, feeding findings back into the pre-silicon environment

Lead and grow the team

Bring a strong point of view on methodology, and be willing to disagree with the team and with peers when the engineering case supports it

Own the direction of an established verification environment — understand the reasoning behind it, then decide what to evolve and what to replace

Lead, coach, and retain principal-level verification engineers; be accountable for their development and continued engagement

Grow the team toward a multi-workstream org: own staffing requirements, leveling, interview loop design, closing senior candidates, and developing technical leads

Own the methodology

Own the DV methodology end to end — verification architecture, reuse strategy, and sign-off criteria

Lead development of test benches, agents, checkers, and stimulus at block, full-chip, system, and gate level

Drive pre-silicon debug and closure in both functionality and performance; own regression health and root-cause discipline

Land new DV methodologies and processes, including AI-assisted verification workflows, to improve execution effectiveness and efficiency

Direct emulation and FPGA prototyping strategy, and own third-party verification IP evaluation and EDA vendor relationships for DV tooling

Partner across the organization

Partner with architecture, design, and software teams to settle requirements and drive DV planning

Work with the compiler and runtime teams to map ML application flows into verification, so silicon is validated against real workloads

Partner with hardware and systems teams on lab validation of first silicon, and represent DV in reviews with physical design, process and quality, and product

Required qualifications

BS in EE, CS, or CE with 12+ years (or equivalent) of industry experience in ASIC design verification

5+ years managing design verification engineers, including hiring and performance management, with experience leading senior and principal-level engineers

Track record of inheriting an established verification environment and evolving it with the team rather than replacing it wholesale

Deep, current technical expertise in verification — able to own methodology, arbitrate testbench architecture, and personally lead debug on the hardest pre-silicon failures

Full-cycle DV from planning through tape-out and into production silicon on at least one complex ASIC or large subsystem

Deep hands-on foundation in SystemVerilog, SVA, Python, and industry verification methodologies such as UVM, OVM, or VMM

Experience through silicon bring-up, including lab functional validation and debugging first-silicon issues to root cause

Working knowledge of machine learning SoCs or microprocessors (CPU/GPU) and modern computer architecture

Excellent communication skills and a track record of building consensus among stakeholders and team members

Preferred qualifications

MS or PhD in EECS with 15+ years of experience in ASIC design verification

Multiple large-scale, high-impact chips led to silicon

Scaling a DV team through a step change in headcount or chip complexity

Owning or directing post-silicon functional validation in a lab environment

Deep understanding of performance verification methodology

High-performance interconnect protocols (PCIe, Ethernet) and memory subsystems

Advanced TSMC nodes and modern multi-die or chiplet verification challenges

Emulation and FPGA prototyping platforms

Managing cross-site or distributed teams

Fluency with Claude or other AI tools applied to verification and flow development

Base Salary Range:

Base Pay Range

$270,000—$340,000 USD