Senior Principal Hardware Emulation Engineer

About the team

The emulation team builds the pre-silicon model of SambaNova's RDU that the software, architecture, and verification teams depend on.

About the role

SambaNova is looking for a Senior Principal Engineer to build and own the hardware emulation models for our next-generation Reconfigurable Dataflow Unit — the silicon behind our AI workload acceleration systems.

Emulation is a development platform here, not a checkbox. Our software teams bring up drivers, runtime, and compiler against the emulation model months before silicon. Our architects measure performance on it. Our verification team runs on it to get through scenarios that simulation cannot reach in useful time. When the model is fast, accurate, and available, three organizations move faster; when it is not, they wait.

Building that model is the core of the job. You will work shoulder to shoulder with the RTL design team to keep the design emulation-compliant, decide where a vendor model will do and where you need to write a custom one, and own the automation that keeps the platform running tests continuously rather than by hand. This is a senior individual-contributor role, and much of its leverage comes through other teams: you will be the person design, verification, and software engineers consult on what emulation can and should do, and the one who holds our emulator vendors to account.

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Responsibilities

Build the models

Develop the emulation model for each new RDU generation: high-performance transactors, behavioral models, and memory models in SystemVerilog and C/C++

Partner with the RTL design team to keep the design emulation-compliant: review RTL and IP for constructs that will not map cleanly to the emulator, and close the gaps by substituting vendor emulation models or hand-coding custom models where no vendor model exists

Own model fidelity: make sure substituted and custom models track design intent closely enough that software, performance, and verification results can be trusted

Influence design decisions upstream so emulation-readiness is designed in rather than worked around

Own the platform, flows, and automation

Own the emulation environment architecture: build and runtime flows, partitioning, compile strategy, clocking, and memory configuration for each chip generation

Build and own the workflows that automate emulation testing on the hardware: job scheduling, regression launch, failure triage, and results reporting, so the platform runs continuously without manual babysitting

Own throughput and capacity: profile and remove bottlenecks in models, transactors, and testbench collateral so turnaround stays fast as the design grows

Own the emulator vendor relationship: drive blocking tool issues to resolution, hold the vendor accountable to our program schedule, and advise on platform selection and capacity investment

Serve the three primary use cases

Software and hardware co-development: deliver and sustain the platform software teams depend on for pre-silicon bring-up of drivers, runtime, and compiler, and debug hardware/software integration failures alongside them

Performance verification: enable workload bring-up, measurement methodology, and reproducible results, and work with architecture to correlate emulated performance against architectural models

Verification acceleration: partner with design verification to move long-running and full-chip regressions onto emulation reliably, including system-level and gate-level scenarios that are impractical in simulation

Silicon debug, secondary to the above: reproduce post-silicon issues on emulation when lab debug needs a controllable, fully visible model

Technical Leadership

Own the emulation methodology and mentor engineers on it, and act as the authority design, verification, and software teams consult when deciding what belongs on emulation

Required Qualifications

BS or MS in EE, CE, or CS with 10+ years (or equivalent) of industry experience, including deep hands-on emulation work

Hands-on expertise bringing up and sustaining designs on an industry-standard emulation platform such as Palladium, Veloce, or Zebu: compile flows, partitioning, debug capabilities, and performance tuning

Strong SystemVerilog together with C/C++, applied to building transactors, behavioral models, memory models, and co-emulation infrastructure

Experience making a design emulation-ready: identifying RTL and IP that will not map to the emulator, and resolving it by substituting vendor emulation models or coding custom models

Track record owning an emulation platform across at least one full chip program, from bring-up through tape-out, including enabling software teams to run a real stack against the pre-silicon model

Track record owning an emulator vendor relationship: driving blocking tool issues to resolution and evaluating and landing new platform capabilities

Experience applying emulation to performance analysis, to accelerating functional verification regressions, or both

Deep debug ability across the hardware/software boundary: able to localize a failure that could be RTL, model, transactor, flow, or software

Scripting and automation in Python and shell: building the regression, scheduling, and triage workflows that keep an emulation platform continuously utilized

Demonstrated technical leadership without formal authority: setting methodology direction across design, verification, and software teams

Preferred Qualifications

MS or PhD in EE, CE, or CS with 12+ years of experience

Depth on Cadence Palladium

Hands-on experience on more than one emulation platform, with judgment about the trade-offs between them

Machine learning accelerators, dataflow architectures, or reconfigurable silicon

High-speed interconnect and memory modeling: PCIe, Ethernet, HBM/DDR

Virtual or hybrid platforms combining emulation with instruction-accurate models

FPGA prototyping platforms and design partitioning for prototyping

Post-silicon debug, reproducing lab failures on a pre-silicon platform

Compiler or runtime software background, or experience embedded on a software team

Fluency with Claude or other AI tools applied to flow development and automation

Base Salary Range:

Base Pay Range

$210,000—$280,000 USD