Principal RTL Design Engineer

About the team

SambaNova's RDU is the processor behind our inference systems, and the RTL design team builds the blocks it's made of: compute datapath, on-chip network, and memory subsystems. The team owns microarchitecture through tape-out, including RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with physical design. Frequency targets are aggressive, so how a datapath gets pipelined and where area buys timing are decided here.

About the role

SambaNova Systems is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL for a major block or subsystem of our next-generation Reconfigurable Dataflow Unit, the silicon behind our AI workload acceleration systems.

This is a senior individual-contributor role with real ownership. You'll take a block from microarchitecture specification through RTL, quality closure, and tape-out, and you'll own the power, performance, and area trade-offs along the way. Frequency targets here are aggressive, so the microarchitectural choices you make (how you pipeline a datapath, where you spend area to buy timing) are the substance of the job, not an afterthought.

You'll work alongside architects, design verification, and physical design engineers to converge functionality and timing, and with software and compiler teams to prototype features that move application-level performance. You'll be one of the engineers who sets the technical bar for digital design here: in reviews, in the methodology the team adopts, and in how the design flow evolves.

Responsibilities

Some of your responsibilities will include:

Own microarchitecture and RTL implementation for a major block or subsystem of the RDU, from specification through tape-out

Define and document microarchitecture specifications for complex digital blocks in compute, memory, or on-chip network subsystems

Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle

Hit aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring

Own PPA for your area: make and defend the power, performance, and area trade-offs using advanced techniques for high-speed design

Drive timing closure with physical design: synthesis, STA, critical-path iteration, and response to floorplan and congestion feedback

Own design quality gates for your area: lint, CDC, LEC, and SystemVerilog Assertions capturing design intent

Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures

Work with architects and software teams to prototype and evaluate features that improve application-level performance

Drive AI, automation, and new EDA tool methodologies into the design flow

Set the technical bar in design reviews and mentor design engineers

Required qualifications

BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design

Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent

High-frequency design experience: datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets

Deep foundation in computer architecture and digital logic design: arbitration, flow control, clock domain crossing, and memory structures

Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC

Physical-design awareness: converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team

Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows

Demonstrated technical leadership without formal authority: setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers

Scripting in Python for design and flow automation

Preferred qualifications

Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem

Industry-standard interconnects and protocols: AXI, PCIe, Ethernet, HBM/DDR

AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures

Formal property checking applied to design intent

Advanced TSMC nodes and multi-die or chiplet design

Performance modeling and analysis to support architectural trade-offs

Fluency with Claude or other AI tools applied to RTL design and flow development

MS or PhD in EE, CE, or CS with 10+ years of experience in ASIC RTL design

Base Salary Range:

Base Pay Range

$180,000—$255,000 USD