Principal Place and Route (PnR) Engineer

About the team

The Place and Route team writes the software that maps dataflow graphs onto SambaNova’s Reconfigurable Dataflow Unit (RDU). Our tools partition each graph, place the pieces on the chip’s compute and memory units, and route the communication between them. The quality of that mapping sets the throughput of the compiled program, including large language model inference and training. We are looking to grow our team with highly motivated engineers who want to utilize advanced algorithms to solve challenging problems.

About the Role

You will develop and tune the partitioning, placement, and routing algorithms that map customer workloads onto the RDU. You will work with the compiler team, hardware architects, and performance engineers to model new hardware constraints and trace throughput gaps back to mapping decisions. Your changes will ship in production releases and show up in measured performance.

Responsibilities

Develop partitioning, placement, and routing algorithms that meet hardware resource constraints and keep compile times practical

Tune PnR results for target workloads, including LLM inference at different batch sizes and concurrency levels

Model new hardware constraints and architecture features in our solvers and heuristics as the chip evolves

Analyze compiled output with performance engineers and trace throughput gaps back to mapping decisions

Build the infrastructure for prototyping, regression testing, and deployment of PnR changes

Work with the compiler and hardware teams to define interfaces and resource models

Required Qualifications

M.S. or Ph.D. in Computer Science, Computer Engineering, or related field

3+ years of experience developing optimization or graph algorithms in industry or research

Expert knowledge of graph algorithms, partitioning algorithms, combinatorial optimization, or MILP solvers

Strong proficiency in C/C++

Familiarity with Python

Experience designing large, highly parallel, performance-sensitive systems

Ability to learn hardware architecture and apply it to improve performance

Experience solving NP-hard problems in practice with heuristics, approximation, or pruned exact methods

Preferred Qualifications

Experience with place and route for FPGAs, CGRAs, or other spatial architectures

Experience with ML compilers such as MLIR, LLVM, TVM, or XLA

Experience with simulated annealing, constraint programming, or SAT/SMT solvers

Familiarity with LLM inference stacks such as vLLM and PyTorch

Publications at venues such as FPGA, DAC, ICCAD, or MLSys

Base Salary Range:

Base Pay Range

$1—$999,999 USD