Design Verification Engineer, New Grad

About the Team

The Design Verification team verifies the RDU, SambaNova's chip for AI workloads. We build SystemVerilog and UVM environments for chip-level control and initialization, including sequencing, state transitions, clocking, and recovery, and work with architects, RTL designers, and firmware engineers.

About the Role

As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out.

Responsibilities

Write and execute verification plans for chip-level control and initialization features

Build SystemVerilog and UVM testbench components, including sequences, checkers, assertions, and functional coverage

Write directed and constrained-random tests to find corner cases

Debug simulation and regression failures with RTL designers

Analyze functional and code coverage and close coverage gaps

Required Qualifications

B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field

Coursework or project experience in digital design and computer architecture

Experience with SystemVerilog or Verilog

Scripting experience in Python, Perl, TCL, or shell

Experience with UVM

Familiarity with constrained-random verification, functional coverage, and assertions

Familiarity with clock domain crossing concepts

Preferred Qualifications

M.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field

Experience using AI tools such as Claude for verification development and debug

Internship experience in design verification

Base Salary Range:

Base Pay Range

$120,000—$150,000 USD