Principal Design Verifiction Engineer

Job Overview

SambaNova Systems is looking for a Principal Design Verification Engineer to own verification for a major subsystem of our next-generation RDU — the reconfigurable dataflow silicon behind our machine learning and AI systems.

This is a senior individual-contributor role with real ownership. You will own the test plan, testbench architecture, coverage model, formal verification and sign-off criteria for your area, and you will be the person the team looks to when the hardest failures need root-causing. You will also shape methodology beyond your own subsystem: the infrastructure, reuse patterns, and verification practices the rest of the team builds on.

You will work alongside principal engineers who have built and evolved this verification environment across several generations of silicon, and with design, architecture, compiler, and runtime teams to make sure the chip is verified against real ML workloads.

Roles and Responsibilities

Define and own the verification execution plan end to end for a major subsystem of the RDU — test plan, testbench architecture, coverage model, formal verification, and sign-off criteria

Serve as the technical authority for verification of your subsystem: review and arbitrate testbench design decisions, and lead debug on the hardest failures

Verify functional and performance behavior

Build the coverage model for your area, set the closure bar, and drive it to closure ahead of tape-out

Own regression health and failure triage for your area — drive root cause, not just reproduction

Develop testbench components, agents, checkers, and stimulus at block, full-chip, system, and gate level

Advance DV methodology beyond your own area — reusable infrastructure, verification IP integration, and AI-assisted verification workflows

Contribute to emulation and FPGA prototyping, and support silicon bring-up and post-silicon debug in the lab

Set the technical bar through design and DV reviews, and mentor engineers to raise the level of the team's verification practice

Minimum Qualifications

BS or MS in EE, CS, or CE with 7+ years (or equivalent) of industry experience in ASIC design verification

Deep hands-on expertise in SystemVerilog and SVA with a standard methodology (UVM, OVM, or VMM), plus scripting in Python and C/C++

Full-cycle DV ownership from test plan through tape-out on at least one complex ASIC or major subsystem, including owning a coverage model to closure

Experience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC

Track record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause

Demonstrated technical leadership without formal authority — setting direction in reviews, arbitrating testbench decisions, and mentoring engineers

Working knowledge of modern computer architecture and of machine learning accelerators or SoCs

Preferred Qualifications

MS or PhD in EE, CS, or CE with 10+ years of experience in ASIC design verification

Depth in high-speed I/O verification — protocol-level verification of PCIe or Ethernet, and memory subsystems such as HBM or DDR

Performance verification methodology — building performance benches and analyzing results, not only functional correctness

Formal verification and assertion-based methods

Experience evaluating, integrating, and validating third-party verification IP

Gate-level simulation and debug

Emulation and FPGA prototyping platforms

Post-silicon lab bring-up and functional validation, debugging first-silicon issues to root cause

Strong understanding of one or more of computation, interconnect, or memory systems

Fluency with Claude or other AI tools applied to verification and flow development

Base Salary Range:

Base Pay Range

$180,000—$225,000 USD