Design Verification Engineer

About the team

The Design Verification team works on the RDU, SambaNova's chip for machine learning and AI workloads. This group focuses on chip-level control and initialization: sequencing, state transitions, clocking, and recovery across multiple subsystems on the chip. You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure. The team works closely with the broader verification organization, so debugging and root-causing issues often means coordinating across groups rather than working in isolation.

About the role

SambaNova Systems is looking for a talented and motivated Design Verification Engineer, DFT to help us build state of the art RDU chips for machine learning and artificial intelligence.

Responsibilities

Some of your responsibilities will include:

Develop and execute comprehensive verification plans for complex chip-level control and initialization features

Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and functional coverage

Verify complex sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems

Develop directed and constrained-random tests to identify architectural and implementation corner cases

Closely work with architects, RTL designers, firmware, and other verification teams to understand design intent and drive verification closure

Debug simulation and regression failures and work with design teams to root-cause and resolve issues

Analyze regression failures, functional and code coverage and drive verification to closure

Required Qualifications

B.S. in Computer Science, Computer Engineering, or related field

5+ years relevant industry experience

Strong understanding of digital design, SoC architecture, and verification methodologies

Strong proficiency in SystemVerilog and UVM is required

Experience with constrained-random verification, functional coverage, and assertion-based verification

Good understanding of chip initialization, control sequencing, clocking, and cross-domain interactions

Strong simulation debug and problem-solving skills

Proficiency in scripting languages, e.g. Python, Perl, TCL and shell scripting, etc. is required

Preferred Qualifications

Familiarity with CDC/RDC concepts and verification methodologies

Fluency in Claude / AI tools for verification development and debug

Base Salary Range:

Base Pay Range

$120,000—$200,000 USD