Sr. Design for Test (DFT) Engineer

As a Design for Test Engineer you will work closely with all disciplines involved in chip design and product operations to design, validate, and deploy test solutions for digital, analog, and photonic logic. You will be involved in a variety of tasks including logic design, validation and logic simulations, scripting, timing closure, post-silicon planning and bring up, and bringing products to market.

Responsibilities

Create new chip, module, and system-level DFT solutions for our highly integrated photonics-based AI platform

Develop and deploy DFT methodologies for our next generation products

Provide architecture for integrated electronics/analog/digital test including ATPG and boundary scan

Work with RTL designers to define front-end integration

Work with physical-design engineers to provide backend integration

Create automated flow that can scale with the team and company

Support initial silicon bring-up through debug

Validate DFT implementation and requirements

Proactively solve problems while managing deliverables in a fast-paced, evolving environment.

Minimum Qualifications:

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

At least 5 years of industry experience working on DFT-related activities for advanced ASIC designs

Proven experience in pre-silicon design activities

Work independently on daily tasks and projects, while seeking guidance for new and unfamiliar assignments.

Experience with scripting languages such as Python or TCL

Solid understanding of DFT concepts such as Scan, ATPG, memory test, and JTAG

Knowledge of Basic SoC Architecture and HDL languages like Verilog

Experience working with commercial EDA DFT tools on MBIST, ATPG, and Boundary Scan.

Preferred Qualifications:

Master degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of industry experience working on ASIC designs with multiple production-quality ASIC tapeouts

Prior experience working on DFT related tasks in either logic design, validation, implementation or pattern generation and coverage analysis

Understanding of industry standards and practices in DFT, including JTAG/BSCAN, at-speed Scan-ATPG, MBIST, and trade-offs between test quality and test time

Ability to conduct experiments during silicon debug, gathering and analyzing data, and utilize scripting to support efficient handling of ATE data

Understanding of Timing, Physical Design, and Power impact of DFT structures

Strong teamwork and communication skills with the ability to collaborate with multiple functional teams across a variety of fields

We offer competitive compensation. The base salary range for this role determined based on location, experience, educational background, and market data.

Salary Range: total compensation goes beyond base salary, it also includes a new hire equity grant, annual performance-based equity, and other rewards that recognize your impact and contribution.

$154,000—$218,000 USD