Research Engineer, Chip Design RL (Reinforcement Learning)

About the RL teams

Our Reinforcement Learning teams lead Anthropic's reinforcement learning research and development, playing a critical role in advancing our AI systems. We've contributed to all Claude models, with significant impacts on the autonomy and coding capabilities of Claude Fable 5 and Opus 4.8. Our work spans several key areas:

Developing systems that enable models to use computers effectively

Advancing code generation through reinforcement learning

Pioneering fundamental RL research for large language models

Building scalable RL infrastructure and training methodologies

Enhancing model reasoning capabilities

We collaborate closely with Anthropic's alignment and frontier red teams to ensure our systems are both capable and safe. We partner with the applied production training team to bring research innovations into deployed models, and are dedicated to implement our research at scale. Our Reinforcement Learning teams sit at the intersection of cutting-edge research and engineering excellence, with a deep commitment to building high-quality, scalable systems that push the boundaries of what AI can accomplish.

About the role

We're hiring for the Code RL team within the RL organization. As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at.

You'll leverage your chip design expertise and turn it into tasks and signals for models to learn from. Specifically, you will:

Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.

Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.

Conduct experiments and shape our roadmap.

Deliver your work into research and production training runs.

Collaborate with other researchers and engineers across and outside Anthropic.

You may be a good fit if you:

Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.

Are fluent with industry EDA tools and processes.

Have taped out chips and have experience going from spec to silicon.

Know how to balance research exploration with engineering implementation.

Are passionate about AI's potential and committed to developing safe and beneficial systems.

Strong candidates may also have:

Experience with reinforcement learning, evaluations or environments.

Built tooling or automation around chip design flows.

Worked on ML accelerators or high-performance compute hardware.

Familiarity with high-level synthesis or architecture simulators.

The annual compensation range for this role is listed below.

For sales roles, the range provided is the role’s On Target Earnings ("OTE") range, meaning that the range includes both the sales commissions/sales bonuses target and annual base salary for the role.

Annual Salary:

$500,000—$850,000 USD